1. Field of the Invention
The present invention relates generally to integrated circuit design, and more specifically to evaluation of nets in crosstalk noise analysis.
2. Description of the Related Art
In modern integrated circuit design, separation between conductor lines (“lines”) is optimized to most efficiently utilize chip area. This optimization often results in closely spaced lines that are susceptible to capacitive coupling. In some instances, capacitive coupling between lines can lead to an adverse crosstalk noise condition. In a crosstalk noise scenario, there is an aggressor net and a victim net. The aggressor net is characterized as having a signal that negatively impacts a signal on the victim net. The adverse crosstalk noise condition may occur when both the aggressor net and the victim net are simultaneously active.
Potential aggressors may be identifiable based on circuit layout, but without further analysis it is not possible to determine whether the potential aggressor nets represent a problem, i.e., whether the potential aggressor nets are active simultaneously with respect to the victim nets. In a typical circuit, there can be hundreds of potential aggressor nets. Additionally, since the circuit design process is iterative by nature, a set of potential aggressor may change during different iterations of the circuit design process.
In view of the foregoing, a method is needed for efficiently identifying potentially problematic aggressor nets.